AO4805 30v dual p-channel mosfet general description product summary v ds i d (at v gs =-20v) -9a r ds(on) (at v gs =-20v) < 15m w r ds(on) (at v gs =-10v) < 18m w 100% uis tested 100% r g tested symbol v ds v gs i dm i as , i ar e as , e ar t j , t stg symbol t 10s steady-state steady-state r q jl mj 1.3 t a =70c junction and storage temperature range -55 to 150 c w 2 power dissipation b p d v 25 gate-source voltage -7 units parameter typ max the AO4805 combines advanced trench mosfet technology with a low resistance package to provide extremely low r ds(on) . this device is ideal for load switch and battery protection applications. v maximum units parameter absolute maximum ratings t a =25c unless otherwise noted -30v drain-source voltage -30 a i d -9 -50 t a =25c t a =70c pulsed drain current c continuous drain current maximum junction-to-lead c/w c/w maximum junction-to-ambient a d 32 90 40 r q ja 48 74 maximum junction-to-ambient a t a =25c avalanche current c 54 avalanche energy l=0.1mh c thermal characteristics a 33 c/w 62.5 g1 s1 g2 s2 d1 d1 d2 d2 2 4 5 1 3 8 6 7 top view soic-8 top view bottom view pin1 g2 d2 s2 g1 d1 s1 rev 7: december 2010 www.aosmd.com page 1 of 5
AO4805 symbol min typ max units bv dss -30 v v ds =-30v, v gs =0v -1 t j =55c -5 i gss 100 na v gs(th) gate threshold voltage -1.7 -2.3 -2.8 v i d(on) -50 a 10 15 m w 12 18 t j =125c 13 20 29 m w g fs 27 s v sd -0.7 -1 v i s -2.5 a c iss 2060 2600 pf c oss 370 pf c rss 295 pf r g 1.2 2.4 3.6 w q g 30 39 nc q gs 4.6 nc q gd 10 nc t d(on) 11 ns t r 9.4 ns t d(off) 24 ns t f 12 ns t rr 30 40 ns q rr 22 nc this product has been designed and qualified for th e consumer market. applications or uses as critical components in life support devices or systems are n ot authorized. aos does not assume any liability ar ising out of such applications or uses of its products. aos reserves the right to improve product design, functions and reliability without notice. r ds(on) static drain-source on-resistance body diode reverse recovery charge i f =-9a, di/dt=100a/ m s maximum body-diode continuous current input capacitance output capacitance turn-on delaytime dynamic parameters turn-off delaytime zero gate voltage drain current gate-body leakage current gate resistance v gs =0v, v ds =0v, f=1mhz v ds =-5v, i d =-9a v gs =-4.5v, i d =-5a v gs =-20v, i d =-9a forward transconductance i s =-1a,v gs =0v diode forward voltage v gs =-10v, v ds =-15v, r l =1.67 w , r gen =3 w turn-on rise time turn-off fall time total gate charge v gs =-10v, v ds =-15v, i d =-9a gate source charge gate drain charge m w electrical characteristics (t j =25c unless otherwise noted) static parameters parameter conditions i dss m a v ds =v gs i d =-250 m a v ds =0v, v gs =25v body diode reverse recovery time drain-source breakdown voltage on state drain current i d =-250 m a, v gs =0v v gs =-10v, v ds =-5v v gs =-10v, i d =-8a reverse transfer capacitance i f =-9a, di/dt=100a/ m s v gs =0v, v ds =-15v, f=1mhz switching parameters a. the value of r q ja is measured with the device mounted on 1in 2 fr-4 board with 2oz. copper, in a still air enviro nment with t a =25c. the value in any given application depends on the user' s specific board design. b. the power dissipation p d is based on t j(max) =150c, using 10s junction-to-ambient thermal resistance. c. repetitive rating, pulse width limited by junct ion temperature t j(max) =150c. ratings are based on low frequency and duty cycles to keep initialt j =25c. d. the r q ja is the sum of the thermal impedence from junction to lead r q jl and lead to ambient. e. the static characteristics in figures 1 to 6 are obtained using <300 m s pulses, duty cycle 0.5% max. f. these curves are based on the junction-to-ambien t thermal impedence which is measured with the devi ce mounted on 1in 2 fr-4 board with 2oz. copper, assuming a maximum junction temperatur e of t j(max) =150c. the soa curve provides a single pulse ratin g. rev 7: december 2010 www.aosmd.com page 2 of 5
AO4805 typical electrical and thermal characteristics 17 52 10 0 18 40 0 20 40 60 80 1 2 3 4 5 6 v gs (volts) figure 2: transfer characteristics (note e) -i d (a) 5 10 15 20 0 3 6 9 12 15 -i d (a) figure 3: on-resistance vs. drain current and gate voltage (note e) r ds(on) (m w ww w ) 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -v sd (volts) figure 6: body-diode characteristics (note e) i s (a) 25c 125c 0.8 1 1.2 1.4 1.6 0 25 50 75 100 125 150 175 temperature (c) figure 4: on-resistance vs. junction temperature (note e) normalized on-resistance v gs =-10v i d =-8a v gs =-20v i d =-9a 5 10 15 20 25 30 35 2 4 6 8 10 -v gs (volts) figure 5: on-resistance vs. gate-source voltage (note e) r ds(on) (m w ww w ) 25c 125c v ds =-5v v gs =-10v i d =-9a 25c 125c 0 20 40 60 80 0 1 2 3 4 5 -v ds (volts) fig 1: on-region characteristics (note e) -i d (a) v gs =-3.5v -4v -6v -10v -4.5v -5v v gs =-20v rev 7: december 2010 www.aosmd.com page 3 of 5
AO4805 typical electrical and thermal characteristics 0 2 4 6 8 10 0 5 10 15 20 25 30 q g (nc) figure 7: gate-charge characteristics -v gs (volts) 0 500 1000 1500 2000 2500 3000 0 5 10 15 20 25 30 -v ds (volts) figure 8: capacitance characteristics capacitance (pf) c iss c oss c rss v ds =-15v i d =-9a 1 10 100 1000 10000 0.00001 0.001 0.1 10 1000 pulse width (s) figure 11: single pulse power rating junction-to- ambient (note f) power (w) t a =25c 0.0 0.1 1.0 10.0 100.0 1000.0 0.01 0.1 1 10 100 v ds (volts) i d (amps) figure 10: maximum forward biased safe operating area (note f) 10 m s 10s 1ms dc r ds(on) limited t j(max) =150c t a =25c 100 m s 10ms 0.001 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 pulse width (s) figure 12: normalized maximum transient thermal imp edance (note f) z q qq q ja normalized transient thermal resistance d=t on /t t j,pk =t a +p dm .z q ja .r q ja t on t p d in descending order d=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse r q ja =90c/w single pulse rev 7: december 2010 www.aosmd.com page 4 of 5
AO4805 vdc ig vds dut vdc vgs vgs qg qgs qgd charge gate charge test circuit & waveform - + - + -10v vdd vgs id vgs rg dut vdc vgs vds id vgs unclamped inductive switching (uis) test circuit & waveforms vds l - + 2 e = 1/2 li ar ar bv dss i ar ig vgs - + vdc dut l vgs isd diode recovery test circuit & waveforms vds - vds + di/dt rm rr vdd vdd q = - idt t rr -isd -vds f -i -i vdc dut vdd vgs vds vgs rl rg resistive switching test circuit & waveforms - + vgs vds t t t t t t 90% 10% r on d(off) f off d(on) rev 7: december 2010 www.aosmd.com page 5 of 5
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